The present invention relates to a method of manufacturing a metal oxide semiconductor device on a semiconductor substrate. The present invention has particular applicability in manufacturing metal oxide semiconductor devices with low gate resistance and low junction capacitance.
Metal oxide semiconductor (MOS) devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate, an ion implanted channel region separating the source/drain regions, and a thin gate oxide and a conductive gate, typically polysilicon, formed above the channel region. Conventional approaches to forming MOS devices typically comprise initially blanket doping the substrate with the intended channel implant before gate oxidation, forming the gate oxide and the gate, then counter-doping the source/drain regions and annealing to electrically activate the implants. Thereafter, refractory metal silicide contacts are formed on the source/drain regions and the top of the gate to reduce the device""s gate and source/drain resistance.
Current demands for miniaturization and increased circuit density have led to a dramatic reduction in feature sizes. However, when feature sizes are scaled to below about 1 xcexcm, the above-described conventional technique results in devices exhibiting undesirably increased junction capacitance due to the presence of the channel dopant in the source/drain regions. Furthermore, demands for increased switching speeds require lower gate resistance, which is difficult to achieve with conventional silicide-capped polysilicon gates.
There exists a need for a method of manufacturing a semiconductor device with channel doping localized under the gate, thereby reducing junction capacitance, and with decreased gate resistance, thereby increasing switching speeds.
An advantage of the present invention is a method of manufacturing a semiconductor device having localized channel doping under the gate while also having lower gate resistance than devices manufactured using conventional techniques.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises forming a silicon nitride layer on a main surface of a semiconductor substrate; forming an opening in the silicon nitride layer to expose a portion of the main surface, the opening corresponding to a dimension of a transistor gate and having substantially vertical side surfaces; forming sidewall spacers on the side surfaces of the opening and extending onto the exposed portion of the main surface; ion implanting impurities into the substrate through the opening to form a threshold implant using the silicon nitride layer and the sidewall spacers as a mask; forming a gate oxide layer on a part of the exposed portion of the main surface not covered by the sidewall spacers; forming a doped polysilicon layer on the gate oxide and the sidewall spacers; and forming a metal layer to fill the opening.
Another aspect of the present invention is a semiconductor device comprising a gate oxide layer on a main surface of a semiconductor substrate, and a gate having outwardly sloping side surfaces and a top surface, the gate comprising a doped polysilicon layer on the gate oxide layer and extending along the side surfaces, and a metal layer on the polysilicon layer and extending to the top surface.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.